Zeroing registers
Zeroing registers
Posted Sep 27, 2021 16:40 UTC (Mon) by arjan (subscriber, #36785)In reply to: Zeroing registers by epa
Parent article: Two security improvements for GCC
zeroing a register is so cheap that cpus do it using various internal shortcuts, usually not even taking up any execution resources
(so on say an Intel Icelake cpu you can do +- 5 per cycle since your bottleneck is elsewhere in the pipeline)
(so on say an Intel Icelake cpu you can do +- 5 per cycle since your bottleneck is elsewhere in the pipeline)
most code doesn't dirty more than 5 to 10, so that could in theory still be 2 cycles. But... in an out of order engine,
in part these will fit otherwise vacant slots (no input dependencies so they can go basically at any time) and often just vanish entirely