The current state of kernel page-table isolation

So forgive the ignorance of a newcomer, but the %5 appears to come from the need to flush TLBs to cross page sets. Intel (as well as AMD) have had advanced virtualization support for a while now (mainly aimed at multiple VM architectures) that allow the TLB to hold "address space identifiers" so that the TLB can, in fact, hold different working sets at the same time, even though only one is active. The idea of that feature was that different VMs could cross from one to the other without the typical TLB flush penalty. However, that feature seems ideal for anytime that two disjoint working sets need to be in use with rapid switching between them. This sounds taylor made for KPTI?

The need to hold disjoint working sets for kernel and user is not a new thing. 360/VM did this, and most virtual paged processors outside of the 80x86 series would simply swap the register that holds the root page table on traps, so that you could implement any level of isolation you wanted (by mapping some, most or all of the pages jointly between page sets).