Lessons from the Novena laptop project

It will, but only if you're using the xc6slx9, and even there it's experimental and doesn't support all the features of the FPGA. It's not an impossible problem, but the bitstream format is proprietary and undocumented and there is a lot of reverse-engineering to be done before we can get from the HDL to a programmed FPGA using only open-source tools.

On the other hand, one can use open tools for everything up to generating the netlist (i.e. the interesting part), and rely on the closed Xilinx tools only for the final conversion from netlist to bitstream.