Hardware pain points for memory management
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The first complaint had more to do with hardware-specific software in the kernel: Rik van Riel noted that the PowerPC architecture code does not implement the translation lookaside buffer flush functions. Some other architectures (such as SPARC) have similar limitations. That makes it hard to do the right thing in generic code. It would be nice, he said, if something could be done to make it easier for architecture-independent code to update page table entries.
Peter Zijlstra asked for a way to invalidate a range of page table entries on the x86 architecture. Another popular request for x86 was the ability to support 64KB pages. Currently, on that architecture, there is no hardware page size between 4KB and 2MB.
Mel Gorman asked for a fast operation to zero-fill a page of memory. This ability could be especially useful for huge pages, which can take a while to overwrite with zeroes. There was some talk about whether non-temporal stores (which can overwrite memory without pushing other data out of the processor caches) would be helpful in this situation. Somebody suggested zeroing pages in the kernel's idle loop, when nothing else is going on, but Christoph Lameter responded that he has tried that and it does not really help.
Other requests included a version of the iret instruction that is less painful (faster) for the page fault handler. There was talk of the cost of responding to events and passing messages between CPUs; a version of the mwait instruction that works in user space was suggested as being possibly helpful. The end result of the session was a wishlist to be taken back to the hardware developers; what will come of that remains to be seen.
[Your editor would like to thank the Linux Foundation for supporting his
travel to the Summit.]
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| Conference | Storage, Filesystem, and Memory-Management Summit/2014 |